UPDATED. 2019-09-17 06:24 (화)
Lee Keun-Taek, Samsung Electronics Master, selects the 'Next-Generation Semiconductor Equipment Demands’
Lee Keun-Taek, Samsung Electronics Master, selects the 'Next-Generation Semiconductor Equipment Demands’
  • Yy Lee
  • 승인 2019.04.01 08:51
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Low dispersion, low defects, and low cost are the key
Lee Keun-Taek, Samsung Electronics Semiconductor Research Center Equipment Technology Development Master
Lee Keun-Taek, Samsung Electronics Semiconductor Research Center Equipment Technology Development Master

Lee Keun-Taek, Samsung Electronics Semiconductor Research Center Equipment Technology Development Master, spoke about the "Next-generation semiconductor equipment prospect" at the seminar on semiconductor and display technology held at the El Tower, Yangjae-dong, Seoul on the 6th.

Master Lee is an equipment development expert. He was selected as the “Master”, the top specialist position at Samsung Electronics’ R & D field, at the end of 2014.

He discussed requirements for next-generation DRAM, NAND flash, and logic production equipment.

Innovations for capacitor production facilities have been required in relation to DRAM. DRAM determines either 0 or 1 based on the charge stored within the capacitor. When the circuit line width is miniaturized, the bottom of the capacitor area should also be narrowed. In this case, the vertical length is increased to secure the space for the capacitor charge storage..

If the bottom is narrow and the vertical length is long, it may be attached to adjacent capacitors during the production or may even collapse. The reason why the recent miniaturization of DRAM is stagnant is that it is difficult to solve the structural problems associated with capacitors.

Master Lee explained, “There must be a material with a very high dielectric permittivity, very sturdy electrode. In addition to the material innovation, we need equipment that can adapt to such advancements.”

Having been converted to a 3D structure, the number of lamination layers of NAND flash is continuously increasing. The issue is the etching process. As the number of layers increases, the hole must be drilled into a deeper level. Overseas competitors produce 3D NAND flash in double stack (2-stack) mode because they failed to solve this issue.

The double stack is a technology that increases the number of layers by attaching two 3D NAND chips that have been finished with hole etching and other processes. An insulating layer exists between them. The double stack requires a greater number of processes and more materials than the single stack method of stacking cells in a single way. This means a cost increase. Samsung Electronics is adhering to the single stack process; however, experts say the company will be forced to introduce a double stack process in the future.

Samsung Electronics plans to produce a logic chip with a gate-all-around (GAA) transistor structure from 3 nanometers. For GAA, the key is locating the current-driven gate path on all sides of the existing square FinFET structure. While the current flows on the three planes of FinFET, GAA allows the current to flow from all sides that cover the gate. The larger the path of current flow, the better the performance.

However, Master Lee said, “Transistors, patterning, and materials (needed to commercialize this technology) are all difficult. Low-resistance contact formation technology, copper and low-K technology development in the area of the ​​back end of line (BEOL) wiring process must be preceded.”


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