Chip design house ASICLAND was developing a new packaging technology to improve the cost of customer TSMC’s chip-on-wafer-on-substrate (CoWoS).
CoWoS has room for improvement in performance and power consumption compared to integrated fan-out and organic substrate package, ASICLAND manager Kang Sung-mo said at a local conference in Seoul hosted by TheElec.
CoWoS also allows for flexible control over the size of the interposer, Kang said, and ASICLAND was developing a new package that improves the cost of the silicon interposer.
CoWoS is an advanced packaging technology used by TSMC that uses silicon interposer and through silicon via.
Interposers are used to connect the logic die with the high bandwidth memory; Nvidia’s A100 and H100 as well as Intel’s Gaudi are made with CoWoS.
Besides silicon interposer, there are other versions of CoWoS that use redistribution layer (RDL) inteposer or those that embed a low-cost silicon bridge with RDL.
ASICLAND’s new package uses an RDL interposer which is considered more cost competitive than a silicon interposer.
The HBM and SoC are on top of the RDL interposer and a silicon bridge is used for the connection between the dies. Kang said ASICLAND also installed a heat spreader.
ASICLAND is the only South Korean design house that works for TSMC; it was selected as a value chain alliance member of the Taiwanese chip giant in 2019. The South Korean chip design house is aiming to list on the Korean exchange later this year.
